Huawei says it expects to design chips with transistor density equivalent to 1.4nm processes by 2031 using a new scaling principle that sidesteps the need for advanced lithography tools restricted by US sanctions.
Summary:
Source: Huawei statement and keynote address at the 2026 IEEE International Symposium on Circuits and Systems, Shanghai
- Huawei unveiled the Tau Scaling Law, a new chip design principle focused on reducing signal travel time rather than shrinking transistors, presented at the ISCAS conference in Shanghai on Monday
- The company projects it can design chips with transistor density equivalent to 1.4nm processes by 2031, close to the expected global frontier for advanced chipmaking by decade-end
- Huawei said it has already designed and mass-produced 381 chips over six years using the Tau Scaling Law framework, across smartphones and AI computing applications
- The Kirin chips due in autumn 2026 will be the first to use a related architecture called LogicFolding, which shortens internal wiring to improve performance
- No independent performance data was provided to support the claims
Huawei has outlined an ambitious plan to reach chip performance equivalent to the global frontier of semiconductor manufacturing by 2031, using a design principle of its own devising that it says can compensate for China’s inability to access the most advanced chip fabrication tools.
The company introduced what it calls the Tau Scaling Law at the IEEE International Symposium on Circuits and Systems in Shanghai on Monday. The concept was presented by He Tingbo, who heads Huawei’s semiconductor business, in a keynote framed as a new path for the industry at a moment when the traditional method of improving chips, shrinking transistors, is running out of road.
The Tau Scaling Law takes a different approach, focusing on cutting the time it takes for signals and data to move through chips and computing systems rather than pursuing geometric miniaturisation. Huawei argues that gains in signal efficiency can deliver improvements in performance and chip density that are functionally comparable to what smaller transistors would achieve through conventional means.
The headline claim is that Huawei expects to design chips by 2031 with transistor density equivalent to 1.4-nanometre processes. That figure matters because 1.4nm is projected to be near the global frontier for advanced chipmaking around the end of the decade, putting Huawei’s target in direct competition with what TSMC and Samsung are expected to be producing through conventional lithography at that point.
The path there is already under way, the company said. Huawei has produced 381 chips over the past six years based on Tau Scaling Law principles, spanning smartphones and AI computing. The next visible milestone is the Kirin chip range due in autumn 2026, which will be the first to incorporate a related architecture called LogicFolding, designed to shorten internal wiring and lift performance.
The projection carries an important caveat. Huawei offered no independent verification of its performance claims, and the gap between design targets and manufacturable silicon at scale remains the central question US policymakers designed their export controls to preserve.
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If Huawei’s Tau Scaling Law delivers on its targets, it represents a meaningful challenge to the assumption that US export controls have effectively capped China’s semiconductor ambitions at the high end. Markets exposed to the conventional chip supply chain, particularly advanced lithography equipment makers, may face a longer-term demand question if scaling through architecture rather than manufacturing process becomes viable
